Source Level Debugging of Verilog Designs PDF

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Författare: Naveed Riaz.
Debugging is a very crucial part of hardware design cycle. Once a design is completed, all the possible faults need to be located and corrected. Although the complexity of hardware design is ever increasing, debugging is still mostly performed manually. Today, debugging has become a very painstaking and time consuming task. Model-based diagnosis provides a solid foundation for automated debugging and fault localization but sometimes the quality of the results is questionable as too many diagnosis candidates are reported. The work presented in this book shows how to apply model-based diagnosis to debugging of synthesizable Verilog designs. Moreover, Two extensions of the model based debugging theory to improve the debugging process in terms of reduction in the number of diagnosis candidates reported, are proposed.

This article relies too much on references to primary sources. This article’s lead section does not adequately summarize key points of its contents. This article has an unclear citation style. The references used may be made clearer with a different or consistent style of citation and footnoting. HDL simulators are software packages that compile and simulate expressions written in one of the hardware description languages. HDL simulation software has come a long way since its early origin as a single proprietary product offered by one company.

Today, simulators are available from many vendors at various prices, including free ones. FPGA vendors do not require expensive enterprise simulators for their design flow. In fact, most vendors include an OEM version of a third-party HDL simulator in their design suite. The bundled simulator is taken from an entry-level or low-capacity edition, and bundled with the FPGA vendor’s device libraries.

Below is a list of various HDL simulators. A simulator with complete design environment aimed at FPGA-applications. Aldec licenses Active-HDL to FPGA-vendors, and the underlying engine can be found in the design-suites of those vendors. While ActiveHDL is a low-cost product, Aldec also offers a more expensive, higher-performance simulator called „Riviera-PRO“. Aeolus-DS is a part of Aeolus simulator which is designed to simulate mixed signal circuit. CVC is a Verilog HDL compiled simulator. CVC has the ability to simulate in either interpreted or compiled mode.

Cadence initially acquired Gateway Design, thereby acquiring Verilog-XL. In response to competition from faster simulators, Cadence developed its own compiled-language simulator, NC-Verilog. It also provides support for the e verification language, and a fast SystemC simulation kernel. Xilinx’s simulator comes bundled with the ISE Design Suite. VHDL and Verilog design entities together.

The first Verilog simulator available on the Windows OS. 1998, which was later acquired by Synopsys in 2002. Synopsys discontinued Purespeed in favor of its well-established VCS simulator. Altera’s simulator bundled with the Quartus II design software in release 11. As one of the low-cost interpreted Verilog simulators, Silos III enjoyed great popularity in the 1990s. Simucad’s most current version, Silos-X, is sold as part of a tool-suite.

Another low-cost VHDL simulator with graphical user interface and integrated waveform viewer. Their web site was not updated for quite some time now. You can no longer purchase the software. The free version does work but you have to request a license via email.

SMASH is a mixed-signal, multi-language simulator for IC or PCB designs. Cycle based simulator originally developed at DEC. The DEC developers spun off to form Quickturn Design Systems. Quickturn was later acquired by Cadence, who discontinued the product in 2005. Speedsim featured an innovative slotted bit-slice architecture that supported simulation of up to 32 tests in parallel. This simulator is available on multi-platform, claiming IEEE 1364-2001 compliance. First described in 1972 paper, used in 1980s by ASIC vendors such as LSI Logic, GE.

Verilogger Extreme is a newer, compiled-code simulator that is Verilog-2001 compliant and much faster than Pro. After its acquisition by Cadence Design Systems, Verilog-XL changed very little over the years, retaining an interpreted language engine, and freezing language-support at Verilog-1995. Cadence recommends Incisive Enterprise Simulator for new design projects, as XL no longer receives active development. It is low-cost and Windows-based only. It boasts a built-in waveform viewer and fast execution.

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